Centered Symmetric Quantization for Hardware-Efficient Low-Bit Neural Networks

Faaiz Asim (Ulsan National Institute of Sience and Technology (UNIST)),* Jaewoo Park (UNIST), Azat Azamat (UNIST), Jongeun Lee (UNIST)
The 33rd British Machine Vision Conference


In extremely low-precision quantization, unequal numbers of positive and negative quantization levels seem quite sub-optimal when dealing with symmetrical data distribution such as weight parameters of a neural network. In this paper, based on an observation that a significant amount of quantization error can be caused by a quantizer with unequal vs. equal numbers of quantization levels, we propose a quantizer that has perfectly zero-centered quantization levels for weight quantization, dubbed Centered Symmetric Quantization (CSQ), with an analysis and empirical quantification of why and how much performance gain CSQ can provide over conventional linear quantization (CLQ). Moreover, noting that it is tricky to implement n-bit CSQ using just n-bit arithmetic hardware, we also propose efficient methods of implementing CSQ using (i) standard multiplication hardware and (ii) bit-wise binarized neural-net hardware. Our experimental results using state-of-the-art quantization-aware training methods on ResNets and MobileNet-v2 show that using CSQ for weight in place of CLQ does offer significant performance advantage at extremely low-bit precision (2~3 bits) without any considerable overhead.



author    = {Faaiz Asim and Jaewoo Park and Azat Azamat and Jongeun Lee},
title     = {Centered Symmetric Quantization for Hardware-Efficient Low-Bit Neural Networks},
booktitle = {33rd British Machine Vision Conference 2022, {BMVC} 2022, London, UK, November 21-24, 2022},
publisher = {{BMVA} Press},
year      = {2022},
url       = {}

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